Conventionally, semiconductor storage devices incorporated into system LSIs with finer design rules (for example, see Japanese patent laid-open publications including Japanese Patent Laid-Open No. 7-307091 and Japanese Patent Laid-Open No. 2002-298579) are configured as shown in FIG. 4.
FIG. 4 is a block diagram showing the configuration of a conventional semiconductor storage device. In FIG. 4, reference numeral 1 denotes a memory cell, reference numeral 2 denotes a sense circuit, reference character WL denotes a word line, reference character BL denotes a bit line, reference numeral 3 denotes a row decoder circuit, and reference numeral 4 denotes a level shifter.
The memory cell 1 is a typical DRAM memory cell. In order to charge a capacitor from an N-channel transistor, a voltage higher than the potential of the bit line BL has to be applied as the potential of the word line WL. Further, in order to suppress the leakage voltage of the N-channel transistor to improve charge retention characteristics, the word line WL generally has a negative voltage when not accessed.
Thus it is necessary to dispose a high breakdown-voltage transistor in the row decoder circuit 3. The high breakdown-voltage transistor has a thicker gate oxide film than a transistor disposed in the sense circuit 2 and so on. For this operation, the level shifter 4 is disposed in the row decoder circuit 3 to operate the word line WL at a control circuit voltage as high as the voltage of the bit line BL.
FIG. 5 is a circuit diagram showing the configuration of the row decoder circuit 3 in the conventional semiconductor storage device. In FIG. 5, reference numeral 11 denotes an output inverter, reference numeral 12 denotes a high-breakdown-voltage transistor region where the gate oxide film has a large thickness, reference numeral 13 denotes an NAND element, reference numeral 14 denotes an inverter, and reference character AD denotes a row address signal.
The level shifter 4 is fed with a signal obtained by decoding the row address signal AD through the NAND element 13 and the inverter 14. The input level of the signal is equivalent to a control circuit voltage as high as the voltage of the bit line BL, and thus is relatively low. The output of the level shifter 4 is outputted to the output inverter 11. The output of the output inverter 11 is connected to the word line WL. The output inverter 11 is fed with a high level VPP and a low level VNWL of the word line WL. The level shifter 4 and the output inverter 11 are disposed in the high-breakdown-voltage transistor region 12 where the gate oxide film has a large thickness.
The following is the operating principles of the semiconductor storage device configured thus.
In the sense circuit 2 for reading the data of the memory cell 1, a high density transistor is used for finer design rules in, e.g., the 45-nm generation. The center value of an applicable voltage is about 1.0 V to 1.2 V and the gate oxide film is about 1.5 nm in thickness. The word line WL requires 2.0 V which is increased from the center value by the threshold voltage of the N-channel transistor of the memory cell 1, and the negative voltage of the word line WL is set at about −0.4 V in consideration of characteristics (GIDL) that the leakage current of a drain is increased by the application of a gate voltage at a low level. Thus generally, the high breakdown-voltage transistor in the row decoder circuit 3 includes a gate oxide film which is at least 5 nm in thickness, and has a threshold voltage of at least 0.6 V.
In this case, in order to operate the level shifter 4, a stable voltage of at least 0.6 V has to be supplied to the input of the level shifter 4. Since the input has a center value of about 1.0 V to 1.2 V, the worst voltage is about 0.8 V. The level shifter 4 has a cross-coupled configuration of a P-channel transistor. The level shifter 4 is operated such that the drain voltage of the P-channel transistor is reduced to the source potential of an N-channel transistor by the N-channel transistor connected to a side where the P-channel transistor is turned on, so that the cross-coupled phase of the P-channel transistor is inverted and the output is also inverted. Since a high voltage output can be obtained even by a low input voltage, the level shifter 4 configured thus is widely used.
For operations, however, the high level of the input has to be sufficiently higher than the threshold voltage of the N-channel transistor.
However, in the conventional semiconductor storage device, relative to the worst value of 0.8 V at a high level of the input, the transistor composing the level shifter 4 has a threshold voltage of at least 0.6 V in the 45-nm generation and so on responding to finer design rules. Thus the threshold voltage is not sufficiently high.
In the case where the input voltage is close to the threshold value, the size of the N-channel transistor has to be set at least 20 times as large as the size of the P-channel transistor in order to increase the capability of the N-channel transistor relative to the capability of the P-channel transistor, thereby increasing the size and load of the circuit. Thus it is difficult to perform high-speed operations.